Graphics subsystem hardware in a computing device may include several independent graphic engines such as a rendering engine, paging engine, display engine, and the like. A software algorithm implemented as a graphics scheduler may be utilized to schedule the graphics engines to execute multiple graphics workloads, which are executed on graphics hardware.
When the graphics scheduler is executed, for example, by a central processing unit (CPU) of the computing device, the execution of the graphics scheduler on the CPU may impose significant latency overhead due to communication delays between the graphic engines and the CPU. Furthermore, a typical tracking of unreported or dropped workload through full scanning of memory registers may add additional latency overhead.